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| september 2007 rev 6 1/30 1 ST7LNB0V2Y0 diseqc? 2.1 slave microcontroller for lnbs and switchers features clock, reset and supply management ? reduced power consumption. ? safe power on/off management by low voltage detector (lvd). ? internal 8 mhz oscillator communication interface ? one diseqc? 2.1 communication interface analog interface ? 13/18 v voltage detector ? 22 khz tone detector i/o ports ? 8 output ports for control of committed and uncommitted switches ? 1 output port for standby control description the ST7LNB0V2Y0 is an 8-bit microcontroller dedicated to diseqc? slave operation in lnbs and switchers. it is compliant with the diseqc? level 2.1. it also supports backwards compatible mode (13/18 v, 22 khz tone) and toneburst signalling. figure 1. block diagram so16 narrow 8-bit core alu address and data bus reset 8 mhz. rc osc internal clock control v ss power supply lvd v dd switch ports diseqc? 2.1 op[8:1] sby 22khz tone detector 13/18 v detector drx dtx table 1. device summary features orderable part number: ST7LNB0V2Y0m6 packages so16 narrow peripherals diseqc? 2.1 communication interface, 22 khz tone detector, 13/18 v detector operating voltage 4.5 to 5.5 v temperature range -40 to +85 c www.st.com
contents ST7LNB0V2Y0 2/30 contents 1 ST7LNB0V2Y0 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 ST7LNB0V2Y0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 ST7LNB0V2Y0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 ST7LNB0V2Y0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 ST7LNB0V2Y0 switching output modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.1 single polarity output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.2 decoded output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.3 complementary output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 supported diseqc? commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 ST7LNB0V2Y0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 command 0fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 command 0dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5.1 functional ems (electromag netic susceptibility) . . . . . . . . . . . . . . . . . . 18 6.5.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 20 6.6 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ST7LNB0V2Y0 contents 3/30 6.7 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1 data eeprom option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 list of tables ST7LNB0V2Y0 4/30 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. ST7LNB0V2Y0 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. single polarity output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. ST7LNB0V2Y0 diseqc? supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. command 0fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. command 0dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. reply to command 0dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. ST7LNB0V2Y0 eeprom parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. output configuration byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 10. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14. operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15. operating conditions with the diseqc? signalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 16. supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 17. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 18. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 19. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 20. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 21. general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 22. output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 23. asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 24. pin plastic small outline package, 150-mil width, mechanical data. . . . . . . . . . . . . . . . . . . 25 table 25. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 26. soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . . 26 table 27. description of data eeprom option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 28. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ST7LNB0V2Y0 list of figures 5/30 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. so16 narrow pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. ST7LNB0V2Y0 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. typical idd in run vs. fcpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. two typical applications with unused i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. typical ipu vs. vdd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 9. typical vol at vdd=5 v (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. typical vol at vdd=5 v (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 figure 11. typical vdd-voh at vdd=5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. pin plastic small outline package, 150-mil width, package outline . . . . . . . . . . . . . . . . . . . 25 figure 13. option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ST7LNB0V2Y0 pin description ST7LNB0V2Y0 6/30 1 ST7LNB0V2Y0 pin description figure 2. so16 narrow pinout 1. nc = not connected see ta bl e 2 for a description of the pin functions. table 2. ST7LNB0V2Y0 pin functions pin number function name function description 1 vss ground 2v dd power supply (+5 volts) 3 reset reset (active low) input 4 drx receive input 5 op5 output 5 (uncommitted port) 6 op6 output 6 (uncommitted port) 7 op7 output 7 (uncommitted port) 8 op8 output 8 (uncommitted port) 9 op4 output 4 (so b/a) 10 op3 (1) 1. during normal operation this pin must be pulled-up inte rnally or externally to avoid entering icc mode unexpectedly during a reset. usi ng an external pull-up of 10 k ? is mandatory in noisy environment. in the final application, a reset will put th e pin back in input pull-up configurat ion even if it was configured as an output. output 3 (sb/sa) 11 op2 output 2 (h/v) 12 op1 output 1 (hi/lo) 13 sby standby 14 dtx diseqc? data transmit output 15,16 - not used (2) 2. unused pins must be tied to ground. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v ss v dd drx op8 op7 op6 op5 reset nc (1) nc (1) op4 op3 op2 op1 sby dtx ST7LNB0V2Y0 st7lnb0v2 y0 implementation 7/30 2 ST7LNB0V2Y0 implementation figure 3 shows a typical application circuit for the ST7LNB0V2Y0. figure 3. ST7LNB0V2Y0 typical application circuit 1. the divider chain connected to the drx pin must have the following resistance values: 330k ? and 100k ? . 2. the reset circuitry linked to the reset pin is optional. in fact the st 7lnb0v2y0 has an internal voltage level detector (lvd) which generates a static reset when the v dd supply is below a threshold voltage of 4.1 v. 3. the diseqc signalling must have a tone frequency of 2 2khz ( 20%) and an amplitude exceeding 150 mv peak to peak. 4. when the lvd is enabled (default stat e), it is mandatory not to connec t a pull-up resistor. a 10 nf pull- down capacitor is recommended to filter noise on the reset line. ST7LNB0V2Y0 control f-connector 4.7k (4) 10n 100k 330k lnb / switcher control sby lnb / switcher (uncommitted sw) (committed sw) 180pf 2n2222 optional vss vdd reset drx op5 op6 op7 op8 nc dtx sby op1 op2 op3 op4 nc ST7LNB0V2Y0 functional description ST7LNB0V2Y0 8/30 3 ST7LNB0V2Y0 functional description 3.1 ST7LNB0V2Y0 configuration unlike the original slave microcontroller described in the eutelsat diseqc slave microcontroller specifications version 1.0, the ST7LNB0V2Y0 does not scan the control pins in order to determine the slave configuration. instead all configuration parameters must be programmed for each specific application, and an option list (see section 8: device configuration ) must be filled-in to program the ne cessary options at the manufacturing stage. the slave configuration parameters are the following: the diseqc? slave address: 11h for an lnb, and 15h for a switcher the local oscillator frequ ency table entry numbers the diseqc? configuration byte (refer to page 15 of diseqc slave microcontroller specifications ) the output mode (see next paragraph) 22 khz tone use in backwards compatible mode (sb/sa or hi/lo switching) standby pin use 3.2 ST7LNB0V2Y0 switching output modes the ST7LNB0V2Y0 has 8 pins, op1 to op 8 available to provide ?ttl? logic levels to operate switches. the switches can be are used to select various signal conditions and sources (for example horizontal po larization, or satellite position). as listed in ta bl e 2 , the committed output port is composed of op1 to op4 and the uncommitted output port is composed of op5 to op8. depending on the application hardware, the switching control pins op1 to op8 may be operated differently. three possible output modes can be configured: 3.2.1 single pola rity output mode in this mode each pin can be controlled individually as described in ta bl e 3 : table 3. single polarity output mode function name function description op4 so b/a op3 sb/sa op2 hor/ver op1 hi/lo op5 sw5 op6 sw6 op7 sw7 op8 sw8 ST7LNB0V2Y0 ST7LNB0V2Y0 functional description 9/30 3.2.2 decoded output mode this mode offers the possibility to demultip lex three adjacent comm itted or uncommitted control lines (hi/lo, sb/sa and sob/a) in order to have a 1 of 8 demux on the output port op1 to op8. for more details refer to page 10 of diseqc? slave microcontroller specifications. it is also possible to have a 1 of 4 demux by decoding only 2 control lines, sb/sa and so b/a for controlling a 1 of 4 switcher for example. 3.2.3 complementary output mode in this mode the state of the uncommitted switching output port pins is the complementary of the state of the committed output ports pins. for more details refer to page 14 of diseqc? slave microcontroller specifications. supported diseqc? commands ST7LNB0V2Y0 10/30 4 supported diseqc? commands table 4. ST7LNB0V2Y0 diseqc? supported commands command number (hex byte) command name command function 00h reset reset diseqc? microcontroller 01h clr reset clear the reset flag 02h standby switch peripheral power off 03h power on switch peripheral power supply off 04h set cont set contention flag 05h contend return address only if contention flag is set 06h clr cont clear contention flag 07h address return address unless contention flag is set 08h move c change address only if contention flag is set 09h move change address unless contention flag is set 10h status read status register 11h config read configuration register 14h group 0 read switching state (committed port) 15h group 1 read switching state (uncommitted port) 20h set lo select the low local oscillator frequency 21h set vr select the vertical polarization 22h set pos a select satellite position a 23h set so a select switch option a 24h set hi select the hi local oscillator frequency 25h set hl select the horizontal polarization 26h set pos b select satellite position b 27h set so b select the switch option b 28h set s1 a select switch s1 input a 29h set s2 a select switch s2 input a 2ah set s3 a select switch s3 input a 2bh set s4 a select switch s4 input a 2ch set s1 b select switch s1 input b 2dh set s2 b select switch s2 input b 2eh set s3 b select switch s3 input b 2fh set s4b select switch s4 input b 38h write n0 write to port group 0 (committed switches) 39h write n1 write to port group 1 (uncommitted switches) ST7LNB0V2Y0 supported diseqc? commands 11/30 note: after a power-on, the ST7LNB0V2Y0 responds to backwards compatible signalling (13/18 v, 22 khz, tone burst) until a valid diseqc frame is detected. a reset command must be sent in order to return to backwards compatible mode. 51h lo read current l.o frequency table entry number 52h lo lo read lo l.o frequency table entry number 53h lo hi read hi l.o frequency table entry number table 4. ST7LNB0V2Y0 diseqc? supported commands (continued) command number (hex byte) command name command function ST7LNB0V2Y0 configuration ST7LNB0V2Y0 12/30 5 ST7LNB0V2Y0 configuration a dedicated diseqc command is implemented to configure the ST7LNB0V2Y0 to the required target application. this configuration is stored in the ST7LNB0V2Y0 embedded eeprom location. 5.1 command 0fh ST7LNB0V2Y0 devices are shipped to customers with a default parameter value. these parameters can be updated using a dedicated 0fh diseqc command. the format of this command is described in ta bl e 5 where ?data? is the parameter value to be programmed at the ?index? location as shown in ta b l e 8 . note: the special command e0 xx 0f ff ff protects the eeprom data from any subsequent write access (where xx is the corresponding diseqc slave address). 5.2 command 0dh a dedicated 0dh command ha s been added to read a pa rameter located in eeprom. the format of this command is described in ta b l e 6 where ?index? is the address of the byte to be read in eeprom area. the format of the reply frame is given in ta bl e 7 where ?data? is the byte read from eeprom: table 5. command 0fh e0h diseqc slave address 0fh index data table 6. command 0dh e2h diseqc slave address 0dh index table 7. reply to command 0dh e4h data ST7LNB0V2Y0 ST7LNB0V2Y0 configuration 13/30 timings the time required to update a byte parameter (write followed by read operation) is 130 ms; whereas the time required to update all the parameters is about 3.5 s. : table 8. ST7LNB0V2Y0 eeprom parameters index parameter description default value 00 slave address diseqc slave address (00 to ffh) (1) 1. besides the address defined in the eeprom at inde x 00h, addresses 10h and 00h are recognized also as valid addresses. 14h 01 l.o frequencies (2) 2. l.o frequencies: local osci llator table entry numbers. - high nibble: high l.o frequency - low nibble: low l.o frequency 00h 02 output configuration see ta b l e 9 0ah 03 serial / version number user c an enter a value:0000h to ffffh 1bh, see note 4 04 ffh table 9. output configuration byte (1) 1. if neither the decoded mode nor the complementary mode is set then the single polarity mode is selected by default. bit number bit description value 0 22 khz use 0: high/low switching 1: sb/sa switching [1:4] decoded mode selection 0: mode not selected [1 to 8]: decoded mode number 5 complementary mode selection 0: mode not selected 1: mode selected 6 2 lines decoded mode selection 0: mode not selected 1: mode selected 7 not used 0 electrical characteristics ST7LNB0V2Y0 14/30 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25 c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a =25 c, v dd =5 v for the 4.5 v v dd 5.5 v voltage range. they are given only as design guidelines and are not tested. 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 4 . figure 4. pin loading conditions c l st7 pin ST7LNB0V2Y0 electrical characteristics 15/30 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 5 . figure 5. pin input voltage 6.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in st7 pin table 10. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 7.0 v v in input voltage on any pin (1)(2) 1. directly connecting the i/o pins to v dd or v ss could damage the device if an unexpected change of the i/o configuration occurs (for example, due to a corrupt ed program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10k ? for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics ST7LNB0V2Y0 18/30 6.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consumption, the two current values must be added. figure 6. typical i dd in run vs. f cpu 6.5 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 6.5.1 functional ems (elect romagnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. table 16. supply current (1) 1. t a = -40 to +125 c unles s otherwise specified. symbol parameter conditions typ max unit i dd supply current in run mode (2) 2. cpu running with memory access, all i/o pi ns in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin ) driven by external sq uare wave, lvd disabled. v dd =5.5v, f cpu =8mhz 4.50 7 ma supply current for lnb or switcher applications (3) 3. data based on typical ST7LNB0V2Y0 lnb or switcher applicat ion software running. 20 0.0 1.0 2.0 3.0 4.0 5.0 2.4 2.7 3.7 4.5 5 5.5 vdd (v) idd (ma) 8mhz 4mhz 1mhz ST7LNB0V2Y0 electrical characteristics 19/30 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forc ing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). 6.5.2 electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the boar d and the loading of each pin. table 17. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-2 2b v fftb fast transient voltage burst limits to be applied through 100 pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-4 3b table 18. emi characteristics (1) symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 1/4mhz 1/8mhz s emi peak level v dd = 5v, t a = +25 c, so16 package, conforming to sae j 1752/3 0.1 mhz to 30 mhz 8 14 db v 30 mhz to 130 mhz 27 32 130 mhz to 1 ghz 26 28 sae emi level 3.5 4 - 1. data based on characterization results, not tested in production. electrical characteristics ST7LNB0V2Y0 20/30 6.5.3 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electrostatic discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the mi cro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. i/o port pin characteristics 6.6 i/o port characteristics 6.6.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. table 19. absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 4000 v table 20. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). lu static latch-up class t a = +25 c a dlu dynamic latch-up class v dd = 5.5 v, f osc = 4mhz, t a = +25 c a ST7LNB0V2Y0 electrical characteristics 21/30 figure 7. two typical applications with unused i/o pin figure 8. typical i pu vs. v dd with v in =v ss table 21. general characteristics symbo l parameter conditions min typ max unit v il input low level voltage 0.3v dd v v ih input high level voltage 0.7v dd v hys schmitt trigger voltage hysteresis (1) 1. data based on characterization results, not tested in production. 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption (2) 2. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure 7 ). data based on design simulation and/or technology characte ristics, not tested in production. floating input mode 200 r pu weak pull-up equivalent resistor (3) 3. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics described in figure 8 ). v in =v ss , v dd =5v 50 120 250 k ? c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time (1) c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time (1) 25 10 k ? unused i/o port ST7LNB0V2Y0 10 k ? unused i/o port ST7LNB0V2Y0 v dd 0 10 20 30 40 50 60 70 80 90 2 2 .5 3 3 .5 4 4.5 5 5 .5 6 vdd(v) ip u (u a ) ta=140c ta=95c ta=25c ta=-45c electrical characteristics ST7LNB0V2Y0 22/30 6.6.2 output driving current subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 9. typical v ol at v dd =5 v (standard) figure 10. typical v ol at v dd =5 v (high-sink) table 22. output driving current characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk must always respect t he absolute maximum rating specified in section table 11. and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 9 ) v dd =5v i io =+5 ma 1.0 v i io =+2 ma 0.4 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 10 ) i io =+20 ma 1.3 i io =+8 ma 0.75 v oh (2) 2. the i io current sourced must always respect the absolute maximum rating specified in section table 11. and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 11 ) i io =-5 ma v dd -1.5 i io =-2 ma v dd -0.8 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.0112345 lio (ma) vol at vdd=5v -45c 0c 25c 90c 130c 0.00 0.50 1.00 1.50 2.00 2.50 6 7 8 9 10152025303540 lio (ma) vol (v) at vdd=5v (hs) -45 0c 25c 90c 130c ST7LNB0V2Y0 electrical characteristics 23/30 figure 11. typical v dd -v oh at v dd =5 v 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 -0.01-1-2 -3-4-5 lio (ma) vdd-voh at vdd=5v -45c 0c 25c 90c 130c electrical characteristics ST7LNB0V2Y0 24/30 6.7 control pin characteristics table 23. asynchronous reset pin (1)(2)(3) symbol parameter conditions min typ max unit v il input low level voltage 0.3v dd v v ih input high level voltage 0.7v dd v hys schmitt trigger voltage hysteresis (4) 1v v ol output low level voltage (5) v dd =5 v i io =+5 ma 0.5 1.0 v i io =+2 ma 0.2 0.4 r on pull-up equivalent resistor (6)(4) v dd =5 v 20 40 80 k ? t w(rstl)out generated reset pulse duration internal reset sources 30 s t h(rstl)in external reset pulse hold time (7) 20 s t g(rstl)in filtered glitch duration (8) 200 ns 1. the output of the external reset circuit must have an open-dra in output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). 2. whatever the reset source is (internal or exter nal), the user must ensure that the level on the reset pin can go below the v il max. level specified in section table 23. on page 24 . otherwise the reset will not be taken into account internally. 3. because the reset circuit is designed to allo w the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-up fo r example) is less than the abs olute maximum value specified for i inj(reset) in section table 11. on page 16 . 4. data based on characterization results, not tested in production. 5. the i io current sunk must always respect the absolute maximum rating specified in section table 11. and the sum of i io (i/o ports and control pins) must not exceed i vss . 6. the r on pull-up equivalent resistor is based on a resi stive transistor. specified for voltage on reset pin between v ilmax and v dd 7. 4. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. 8. the reset network protects t he device against parasitic resets. ST7LNB0V2Y0 package characteristics 25/30 7 package characteristics 7.1 package mechanical data figure 12. pin plastic small outline package, 150-mil width, package outline table 24. pin plastic small outline package, 150-mil width, mechanical data dim. mm inches min typ max min typ max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 9.80 10.00 0.386 0.394 e 3.80 4.00 0.150 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n16 0016020 e h a1 c 45 a a1 b d e 16 9 1 8 l package characteristics ST7LNB0V2Y0 26/30 7.2 thermal characteristics 7.3 soldering information in order to meet environmental requirements, st offers the ST7LNB0V2Y0 in ecopack ? package. the package have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at www.st.com , together with specific techni cal application notes covering the main technical aspects related to lead-free conversion (an2033, an2034, an2035, an2036). backward and forward compatibility the main difference between pb and pb-free soldering process is the temperature range. ecopack lqfp, sdip, so and qfn20 packages are fully compatible with lead (pb) containing soldering process (see application note an2034) tqfp, sdip and so pb-packages are compatible with lead-free soldering process, nevertheless it's the customer's duty to verify that the pb-packages maximum temperature (mentioned on the inner box label) is compatible with their lead-free soldering temperature. ) table 25. thermal characteristics symbol ratings value unit r thja package thermal resistance (junction to ambient) 85 c/w t jmax maximum junction temperature (1) 1. the maximum chip-junction temperature is based on technology characteristics. 150 c p dmax power dissipation (2) 2. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user with the formula: p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power di ssipation depending on the ports used in the application. 300 mw table 26. soldering compatibility (wave and reflow soldering process) package plating material devices pb solder paste pb-fr ee solder paste sdip & pdip sn (pure tin) yes yes (1) 1. assemblers must verify that the pb-package maxi mum temperature (mentioned on the inner box label) is compatible with their lead-free soldering process. qfn sn (pure tin) yes yes (1) lqfp and so nipdau (nickel-palladium-gold) yes yes (1) ST7LNB0V2Y0 device configuration 27/30 8 device configuration 8.1 data eeprom option bytes fam option byte: device family address 11h: normal lnb 15h: normal switcher lofreq option byte local oscillator frequency table entry number this byte indicates the valu e of a lnb local oscillator: lowest nibble = lo local oscilla tor frequency table entry number highest nibble = hi local oscillato r frequency table entry number note: see table 2 on page 8 of the eutelsat diseqc slave microcontroller specifications version 1.0 . param option byte: output mode and 22 khz tone use (hi/lo or sb/sa) bit 7:8 = not used bit 6 = decoded mode with only two lines ( the lowest line of a selection group is kept low ) 0: decoded mode with only two lines not selected 1: decoded mode with only two lines selected bit 5 = complementary mode selection 0: complementary mode not selected 1: complementary mode selected bit 4:1 = decoded mode number 0: decoded mode not selected 1 to 8: decoded mode number (refer to table 5a on page 11 of the eutelsat diseqc slave microcontroller speculations version 1.0. bit 0 = 22 khz tone use 0: 22 khz tone use for hi/lo switching in backwards compatible mode 1: 22 khz tone use for sb/sa switching in backwards compatible mode note: if neither a decoded mode nor a complementary output mode is selected, the output mode is the single polarity output mode (refer to table 3: single polarity output mode ). table 27. description of data eeprom option bytes byte name description address fam device family address (11h:lnb; 15h: switcher) 1002h lofreq local oscillator frequency table entry numbers 1003h param output mode and 22 khz t one use (hi/lo or sb/sa) 1004h device configuration ST7LNB0V2Y0 28/30 figure 13. option list ! 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'!4 #4% 5# / 67 (# $# # / 67 ' ( ) $# ' $, %"/ #$ 4 $ '%5# / 67 ........................../.......................... #$$ '&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& # &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& &&&&&&&&&&& !' % &&&&&&&&&&&&&& 4 #8'4# ) 4 > % #'#=) # #'4 =%#$ 888&&(#$ ST7LNB0V2Y0 revision history 29/30 9 revision history table 28. document revision history date revision changes 1.0 initial release sep-04 2.0 first release on st.com dec-04 3.0 changed note 4 and added ?optional? in figure 3 section figure 3.: ST7LNB0V2Y0 typical application circuit on page 7 added default values in table 8: ST7LNB0V2Y0 eeprom parameters 12-oct-05 4.0 changed package name to so16 narrow 03-jan-06 5.0 product code changed to ST7LNB0V2Y0 to reflect upgrade in firmware. 20-sep-07 6.0 document reformatted. root part number st7lnb0 changed to ST7LNB0V2Y0. capacitor changed from 2.2 nf to 180 pf in figure 3: ST7LNB0V2Y0 typical application circuit . updated note 1 below table 15: operating conditions with the diseqc? signalling . ecopack package description updated in section 7.3: soldering information . removed note 3 below table 22: output driving current characteristics . ST7LNB0V2Y0 30/30 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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